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Author Topic: Merry Christmas - O2EM 1.20 (with C7420 emulation)  (Read 33099 times)
manopac
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« Reply #45 on: February 17, 2015, 10:21:18 AM »

as far as I can remember that was one of the changes I did from 1.18 to 1.20 - write to the gfx registers is only possible now when the screen is off (like on the real hardware) - it made a lot of things work in the emulator that did not work on the real hardware, making it tough to properly develop ;-)
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Sorex
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« Reply #46 on: February 17, 2015, 11:45:06 AM »

the only "issue" I've found is that I need to add -nosound & -novoice or the startup is slower.

shouldn't -nosound include the no voice aswell?
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Sorex
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« Reply #47 on: February 17, 2015, 11:46:11 AM »

it made a lot of things work in the emulator that did not work on the real hardware, making it tough to properly develop ;-)

yeah, best practice coding ain't always bad Wink
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manopac
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« Reply #48 on: February 17, 2015, 12:02:07 PM »

just checked (in the changelog that is in the docs directory of the emu ;-) )

1.18.1
   - read/write from/to certain registers (unused, foreground, grid) behaves more like original now - this might make some programs that work on O2em but not original systems stop working (but that is as its supposed to be)

as for the novoice-switch / nosound-switch - I believe those are separate switches, no idea why it was initially implemented that way
but it should make no noticeable difference if you run o2em with or without it ... might have to look in the startup procedure some time ...
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Sorex
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« Reply #49 on: February 17, 2015, 03:40:40 PM »

It takes 1-2 seconds to init the sound on my machine at home and on this faster machine.

turning it of makes o2em open instantly.
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goldenband
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« Reply #50 on: February 17, 2015, 08:00:20 PM »

the NSC800 is implented in MESS as far as I recall, but somehow it's not working properly.

FWIW, when I checked the MESS docs they said:

"Chess needs emulation of the C7010 Chess Module, which had a NSC800 CMOS microprocessor, which gave the G7000 extra CPU and memory."

Older docs have a note that someone "Added NSC800 CPU emulation to the Z80 core", I assume for general use. So I guess the processor itself is already supported, as you say; the question is what's left to do to make the darn thing work.  Wink
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ssj
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« Reply #51 on: February 22, 2015, 07:00:13 AM »

Maybe try asking in the MESS forums? Smiley
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Sorex
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« Reply #52 on: February 25, 2015, 08:29:23 PM »

@manopac : are the dots on the right side of the outer left "cells" normal behaviour?

https://www.dropbox.com/s/w18qybxz564ztih/grid_fill.png?dl=0
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Sorex
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« Reply #53 on: February 25, 2015, 08:38:00 PM »

nevermind, I had another interpretation of "horizontal" Smiley

the line is horizontal bit the bit place go down and not to the right.

and vertical cases the fill apparently and adding horizontal aswell add that fat dot.
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tigrou
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« Reply #54 on: August 24, 2015, 10:06:23 PM »

@manopac :
what about creating a GitHub repository with this new version of O2EM (so you can track changes and other developers can participate).

I was unaware of that special version it until i got there. On GitHub it will be probably more visible.

also : i took a look at sound emulation problem in many games : take a look here https://sourceforge.net/p/o2em/bugs/5/
It's easy to fix.

I was wondering where did Pol Wilbert (the author of the odyssey emulation on MESS/MAME) found out how the noise / LSFR is implemented.

See his comment in i8244.c :

Code:
/* Noise tap is on bits 0 and 5 and fed back to bits 15 (and 23!) */

There is no documentation to be found on that 8244 intel chip Sad

I tried to contact him but it seems he keeps his email private.

Best information about sound I found so far is here : http://www.atarihq.com/danb/files/o2doc.pdf
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Rene_G7400
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« Reply #55 on: August 25, 2015, 09:20:25 AM »


This topic has more information about the 8244:

http://videopac.nl/forum/index.php?topic=1751.0



I was wondering where did Pol Wilbert (the author of the odyssey emulation on MESS/MAME) found out how the noise / LSFR is implemented.

See his comment in i8244.c :

Code:
/* Noise tap is on bits 0 and 5 and fed back to bits 15 (and 23!) */

There is no documentation to be found on that 8244 intel chip Sad

Best information about sound I found so far is here : http://www.atarihq.com/danb/files/o2doc.pdf
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tigrou
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« Reply #56 on: August 25, 2015, 11:55:10 AM »


This topic has more information about the 8244:

http://videopac.nl/forum/index.php?topic=1751.0


Yes you are right. Pol probably used this to implement his odyssey emulation on MESS (for both audio and video)

From odyssey2_timing.txt :

Quote
The feedback taps are bits 0 and 5 of register A9.  These two bits are XOR'd and then passed on to bit 7 of A7 *and* A8. Bit 0 of A9 is still output to the audio output.

    A8        A9
[76543210][76543210]-> audio output
 ^           |    |
 | /---|-----/    |
 \-|xor|          |
   \---|----------/

This results in a noise period of 16383.

So basically kevtris hook up a logic analyser to find out how the chip works (since intel datasheet is nowhere to be found). Brilliant.
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gertk
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« Reply #57 on: August 25, 2015, 05:50:20 PM »

This is what the MCS-48 doc says about the sound system:

SOUND SYSTEM
The sound system generates a duty cycle modulated square wave from which an audio
signal is extracted by means of an external low pass filter. The control of the
duty cycle is effected by information that is transferred from the microprocessor
to the 8245. This information consists of triple byte groups that determine the
audio frequency and an accompanying 4 bits that determine volume.
The triple byte groups are loaded into three-eight bit shift registers located
on the 8245. Each byte in the group is loaded sequentially into its respective
register during a load interval. All three bytes are loaded in between conse-
cutive shift clock pulses. The concatenation of the three registers results
in a 24 bit string that is shifted out by this shift clock. The resulting
serial pattern of ones and zeroes contains a fundamental band of frequency
components that lie in the audio range. This particular signal is further
“chopped” by a higher frequency that is a multiple of the shift clock. By
duty cycle modulation of this “chopping” signal, the amplitude of the audio
component is varied. There are four control bits that are used to control the
audio level. These bits are loaded into a four bit down counter that is shifted
by the high frequency shift clock. The resulting output is ANDED with the output
from the three concatenated shift registers to produce the composite audio output.
In addition to the four volume control bits, three other control bits are used
to augment the overall operation of the sound system. A noise enable bit enables
a feedback path in the output eight bit shift register, in the 25 bit shift path
to produce the noise component. Simultaneously, the noise is added to the audio
component that is progressing down the shift register.
The shift frequency for the register may be varied between two values by another
control bit. This expedient allows low audio frequencies to be produced with
fewer refresh cycles from the microprocessor than for high frequencies thus, re-
ducing the load on the processor.
For the reproduction of certain audio tones that are subharmonically related to
the shift clock, the need for microprocessor refresh is totally eliminated by
recirculation of the 24 bit shift path.
The format of the sound control word is described below:
7 6 5 4 3 2 1 0
EN X S N V3 V2 V1 V0

Bits 0 – 3 – Volume Bits, collectively as a 4 bit word, these bits define the
output audio level.

Bit – 4 – Noise Enable; controls noise generation and mixing with the audio
signal. Bit 4 = 1, noise on; Bit = 0, noise off.12

Bit 5 – Shift Frequency; determines frequency of shift clock.
Bit 5 = 1, f = 3933Hz. Bit 5 = 0, f = 983Hz.

Bit 7 – Enable sound; 0 = No sound, 1 = sound.

For those modes of operation requiring sound refresh data from the microprocessor,
an interrupt is generated each time that the 24 sound bits have been shifted through
the three eight bit shift registers. A 5 bit counter set to module 24 counts shift
clocks and determines when the interrupt should occur.
The sound shift registers, volume counter and sound control word register are all
individually addressed by the microprocessor for the purpose of loading data. The
address of these elements is shown under the topic of “Address Structure”.
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« Reply #58 on: May 06, 2016, 10:06:48 PM »

I tried pressing F4 while working with Grid Edit to save my grid, but it wouldn't let me type anything. I'm using Windows 10.
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Rafael
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« Reply #59 on: May 07, 2016, 02:46:30 PM »

I tried pressing F4 while working with Grid Edit to save my grid, but it wouldn't let me type anything. I'm using Windows 10.

I really missing it, too Cry
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