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Author Topic: To be sure I do not step on any toes....  (Read 9479 times)
Gorf
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« on: January 03, 2009, 11:55:58 PM »

I'd be interested to know what Soren's/Rene's (or whomever else's)
plans are with addons.

I'd like to design this thing so it wont interfere with any of these addons.

I'd like it to be a through cart type of deal. I'll also stay away from
non standards using things such as using the A10 line. I believe
me that the A10 line is used by the voice module, no?

Do I have any locations to map it to with the voice in circuit?

Do I need to be careful of the G7400 mappings?

I'd like to make this unit completely transparent, yet powerful and useful
to all O2/VP/VP+ fans and developers. I think I can pull it off in a GAL or
two. I have a nice surplus of 270C20 EPROMS that I'll put in. I will do my
best also to keep it affordable as possible for everyone's budget.

This addon would add very useful stuff such as a completely indexed table
look up for the ((CHAR*Cool - (Y/2)) equation and  sincos, sqrt result tables.
There plenty of room left for other tables on a 270C20 without using the
A10 line. You lose access to half the chip but it is what it is. 128k bytes
is quite a lot.....of course if anyone can offer a suggestion as to how to
control that other ROM line to access the upper half of the chip, Im all ears!

 Grin

Thanks......

Steve

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Rene_G7400
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« Reply #1 on: January 04, 2009, 02:19:45 AM »

That might not be an easy task.

Access to the Plus graphics chip of the G7400 is enabled with P15, so that shouldn't be a problem.

This is an overview of carts/modules which use more signals than the regular datalines and addresslines:

(btw.: T0 = pin 1, A10 = pin 10, P14 = pin 11, WR = pin A, CS = pin E)

- The Voice: P14, WR, T0
- Videopac 31 and 40: CS, A10
- Videopac 55, 58, 59, 60: P14, WR
- C7010 Chess: P14, WR, CS
- C7420 Basic: T0, P14, WR, CS
- KTAA: A10
- RAMcart: T0, WR, A10
- Testcart: WR
- MegaCart: WR, CS, A10, P14
- FlashCart: WR, CS, A10, P14, T0

All of these signals are NOT available at the cartridge connector of The Voice. These signals are replaced by signals which are necessary for the communication between the speech chip inside The Voice and the speech ROM inside SID the Spellbinder. (pin B is used for that also.)

Games which don't use The Voice must have pin B connected to ground, otherwise The Voice might produce unwanted sounds. Games which do use The Voice must have pin B unconnected, otherwise The Voice won't work.

For a G7400, games which don't use the Plus graphics must have pin B connected to ground, otherwise the screen will have a black border which might cut-off some graphics. Games which do use Plus graphics must have pin B unconnected, otherwise some VDC graphics and background colors might be visible outside the 320x238 area of the Plus graphics.

The Voice will respond to all addresses between 80h and FFh. If databit 5 = 0, then the Voice will be reset and produce no sound. Addresses E4 and E8-F2 are used for bankswitching, so there will be no sound either.

You don't need to loose ROM space by not using A10. Without A10, you will have ROM banks of 2k (addresses 400h-BFFh). You can use P10 and P11 for bankswitching, or as chip enable signals or for other creative purposes.  Wink
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Gorf
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« Reply #2 on: January 04, 2009, 03:32:23 AM »

That might not be an easy task.

I was afraid you might say that. Tongue

Access to the Plus graphics chip of the G7400 is enabled with P15, so that shouldn't be a problem.

Excellent! That is one less issue to be concerned with.


This is an overview of carts/modules which use more signals than the regular datalines and addresslines:
(btw.: T0 = pin 1, A10 = pin 10, P14 = pin 11, WR = pin A, CS = pin E)
- The Voice: P14, WR, T0
- Videopac 31 and 40: CS, A10
- Videopac 55, 58, 59, 60: P14, WR
- C7010 Chess: P14, WR, CS
- C7420 Basic: T0, P14, WR, CS
- KTAA: A10
- RAMcart: T0, WR, A10
- Testcart: WR
- MegaCart: WR, CS, A10, P14
- FlashCart: WR, CS, A10, P14, T0


Just from looking at the titles of some devices,

Is it correct to say that

Anything with both signals P14 and WR have ram included? (A7 is the chip select)
Anything with all three signals P14, WR and CS have RAM larger than the 128 bytes
OR mapped in another area?

Also CS is now the chip select and A10 is used to access the other
unused 1k block after the normal cart space(it is after the cart space
after the 2k, right?)


****Rene said stuf about voice and Pin B and video distruptions.

If only the old Votrax voice sound ships were stil available somewhere.

I 'd settle the whole voice issue with one of those and emulate the voice unit. However,
it would sound more like Arcade Gorf and Wizard of Wor.

Its it now quite apparent that, with all the above info you just gave me, my device would
be better suited as a cart format and not some add on with a cart through trying to work with
everything out there.

You don't need to loose ROM space by not using A10. Without A10, you will have ROM banks of 2k (addresses 400h-BFFh). You can use P10 and P11 for bankswitching, or as chip enable signals or for other creative purposes.  Wink

This too is good news as it will allow me not to have to waste all that upper ROM
and at the same time add 8x8 mutlipy and divide tables but each with 16 bit results.

Yup....I think a cart format is a better route.

I once again thank you for your most gracious help.

Smiley

Gorf
« Last Edit: January 04, 2009, 03:35:41 AM by Gorf » Logged
Rene_G7400
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« Reply #3 on: January 04, 2009, 12:38:50 PM »

Anything with both signals P14 and WR have ram included? (A7 is the chip select)

Yes, but it might be as little as one single 8 bit latch (to store the current bank number for example: VP55, 58, 59, 60). If P10 or P11 are not used for bankswitching, they can be used as chip select too (Testcart).

Anything with all three signals P14, WR and CS have RAM larger than the 128 bytes
OR mapped in another area?

For C7010 and C7420, these signals together with P10 and P11 are used to control the communication between the 8048 of the console and the Z80 of the module (through I/O latches).

Also CS is now the chip select and A10 is used to access the other
unused 1k block after the normal cart space(it is after the cart space
after the 2k, right?)

Videopac 31 and 40 are 4k. Addresses 400h-FFFh are addressed the normal way (A10 = 0 for 800h-BFFh, A10 = 1 otherwise, A11 = 0 for 400h-7FFh, A11 = 1 for 800h-FFFh). They are read the normal way with PSEN. The remaining address space of the ROM (0-3FFh) is used for data only, and is read with CS (high) and P11 (high). P20 and P21 (= A8 and A9) are used for ROM page selection.

KTAA is 12k. Each bank is 3k (addressed the same way as above), bankswitching is done the normal way with P10 and P11. The remaining four 1k blocks of the 16k ROM are unused. The RAMcart works the same way.
« Last Edit: January 04, 2009, 12:41:38 PM by Rene_G7400 » Logged
Gorf
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« Reply #4 on: January 04, 2009, 02:49:59 PM »

Yes, but it might be as little as one single 8 bit latch (to store the current bank number for example: VP55, 58, 59, 60). If P10 or P11 are not used for bankswitching, they can be used as chip select too (Testcart).

Right as I expected. This will use P10 and P11 for addressing the upper
chunks of the ROM....I will only need two latches....I think.

It will be a 27C040 instead. This will allow for 16 bit answers and I came
up with a better addressing design as well. The way I had it set up was
going to require eevn more instructions to access the upper byte of the
word retrieved but this will now allow me to write lo operand, then write
hi operand, then read low result and finally high result(should I reverse the
endian?)

my plan

80h = operand 1 WO
81h = operand 2 WO
82h = result 1 RO
83h = result 2 RO

I use two latches....connected to A1-A16 of the 27040. These
are fed from writing to operands 1 and 2 ,80h and 81h.
P14 = 0, ~WR = 0


When you read result one(82h), the decode trigger brings the 27040's
A0 line low so you are seeing the first byte of the word. When you read
result two(83H), it will bring the 27040's A0 high so you are seeing the
high byte(or low byte if it is better to reverse the endian).
P14 = 0, ~WR = 1(I am assuming ~WR is high on RAM read?)

You dont happen to have any Xilinx software do you? I have the 9.1 suite
and am using that and the schematic designer.

Once I get something solid, if you have the dev kit, I could send it over to
you and maybe tell me if I'm missing something?

Actually, I think I can export to other schematic formats if you have some
other software.



For C7010 and C7420, these signals together with P10 and P11 are used to control the communication between the 8048 of the console and the Z80 of the module (through I/O latches).

Ok so this does not matter.....again...I've decide to make this a cart format.

It will still have a 'through' but for the sole purpose of pluggin carts made to
use the device....at least for now that is the plan. This way new games can
use the device and it wont interfere with the addres space of the ROM for
carts.


Videopac 31 and 40 are 4k. Addresses 400h-FFFh are addressed the normal way (A10 = 0 for 800h-BFFh, A10 = 1 otherwise, A11 = 0 for 400h-7FFh, A11 = 1 for 800h-FFFh).

They are read the normal way with PSEN.

The remaining address space of the ROM (0-3FFh) is used for data only,
and is read with CS (high) and P11 (high). P20 and P21 (= A8 and A9) are used for ROM page selection.

Do you mean the BIOS or the ROM on the cart? I thought the BIOS was mapped
at 0-300h?

Now Im a bit confused.... Roll Eyes


I know that the 8048 has a 'movp3'(?) instruction for using that area as a data table.

KTAA is 12k. Each bank is 3k (addressed the same way as above), bankswitching is done the normal way with P10 and P11. The remaining four 1k blocks of the 16k ROM are unused. The RAMcart works the same way.

This I understand as the BIOS occuppies what would be those unused 1k blocks....um right?
 Roll Eyes


Perhaps a little clarification on that 0-300h thing.

Tongue


Thanks.
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Rene_G7400
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« Reply #5 on: January 04, 2009, 11:56:49 PM »

(should I reverse the endian?)

Since it's an 8-bit machine, it doesn't really matter, you can just use what's most efficient in your program.

When you read result one(82h), the decode trigger brings the 27040's
A0 line low so you are seeing the first byte of the word. When you read
result two(83H), it will bring the 27040's A0 high so you are seeing the
high byte(or low byte if it is better to reverse the endian).
P14 = 0, ~WR = 1(I am assuming ~WR is high on RAM read?)

Yes, but ~WR is always high, unless there is a write. To do a read, you will need the CS signal, which is (unfortunately) a combination of read and write. So there is a read signal when ~WR = 1 AND CS = 1. (CS = 0 normally.)

You dont happen to have any Xilinx software do you? I have the 9.1 suite
and am using that and the schematic designer.

No, I don't. I haven't done any CPLD or FPGA programming (yet).

Videopac 31 and 40 are 4k. Addresses 400h-FFFh are addressed the normal way (A10 = 0 for 800h-BFFh, A10 = 1 otherwise, A11 = 0 for 400h-7FFh, A11 = 1 for 800h-FFFh).
They are read the normal way with PSEN.

The remaining address space of the ROM (0-3FFh) is used for data only,
and is read with CS (high) and P11 (high). P20 and P21 (= A8 and A9) are used for ROM page selection.

Do you mean the BIOS or the ROM on the cart? I thought the BIOS was mapped
at 0-300h?

Yes, the BIOS is always at 0-3FFh. The 8048 can address a maximum of 4k (without bankswitching), so an external ROM can be no more than 3k. Since 3k ROMs don't exist, you need a 4k ROM, but then you would waste 1k. But Philips had a clever idea to use that 1k part. Like I said, from 400h-FFFh you have the instructions, which are fetched by the 8048 by making it's PSEN output low. But this time, this signal isn't sent to the ROM directly, but is combined with P11 and CS. So the outputs of the ROM will be active when PSEN is low, but also when P11 and CS are both high. This 1k data part of the ROM is read with MOVX A,@R0 instructions. Since you can only address 256 bytes this way, P20 and P21 are set before the read, to set the remaining two address bits.

KTAA is 12k. Each bank is 3k (addressed the same way as above), bankswitching is done the normal way with P10 and P11. The remaining four 1k blocks of the 16k ROM are unused. The RAMcart works the same way.

This I understand as the BIOS occuppies what would be those unused 1k blocks....um right?

Right.
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Gorf
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« Reply #6 on: January 05, 2009, 12:43:12 AM »

Since it's an 8-bit machine, it doesn't really matter, you can just use what's most efficient in your program.

Yes, this is true.

Yes, but ~WR is always high, unless there is a write. To do a read, you will need the CS signal, which is (unfortunately) a combination of read and write. So there is a read signal when ~WR = 1 AND CS = 1. (CS = 0 normally.)


Ok so I just need to AND together those two signals and feed that output to the read decode.
Right now I have ~WR good for the writes, I just need to add those AND's for the READS and
include the CS signal.


No, I don't. I haven't done any CPLD or FPGA programming (yet).

I have tried.....hehe...I can read schematics and put together a circuit using it.
It will actualy work(most of the time Tongue ). However I can't seem to seperate
'hook' the singals together using VHDL......DOH! Shocked

I did get the LED's on my Spartan3E board to do a count. Tongue
Perhaps I need to go back and study that sample again.
Cheesy

As far as getting started, you could download the suite right off the
Xilinx website. Not everything is free but there is enough useful stuff
thre to get you rolling. The non fre stuff usually gives you a 60 day trial
anyway. is you can develope something useful in two months, it would
be helpful. Again, since I lack a real understanding of VHDL, I just use
the schematic editor and it does it for me. Im going to actaully go look
at the code of this project once I am done and see if I can finally get what
I did.

Yes, the BIOS is always at 0-3FFh. The 8048 can address a maximum of 4k (without bankswitching), so an external ROM can be no more than 3k. Since 3k ROMs don't exist, you need a 4k ROM, but then you would waste 1k. But Philips had a clever idea to use that 1k part. Like I said, from 400h-FFFh you have the instructions, which are fetched by the 8048 by making it's PSEN output low. But this time, this signal isn't sent to the ROM directly, but is combined with P11 and CS. So the outputs of the ROM will be active when PSEN is low, but also when P11 and CS are both high. This 1k data part of the ROM is read with MOVX A,@R0 instructions. Since you can only address 256 bytes this way, P20 and P21 are set before the read, to set the remaining two address bits.

Ah I see. I thought you might still be able to use MOVP3 A,@A. I suppose that is out due
to the way the signals work out on the cart?

Excellent! I hope I can repay by making something very cool which will
(hopefully) benefit the O2 community.
Smiley
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Rafael
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« Reply #7 on: January 06, 2009, 01:10:28 AM »


Excellent! I hope I can repay by making something very cool which will
(hopefully) benefit the O2 community.
Smiley

Good luck in your project, we?ll waiting a new great game.
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Gorf
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« Reply #8 on: January 06, 2009, 03:26:03 AM »

Thanks Rafael! I like those screen shots you got on your web site.
I only wish I remembered my Spanish classes. Smiley
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Rafael
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« Reply #9 on: January 06, 2009, 09:47:33 PM »

Thanks Rafael! I like those screen shots you got on your web site.
I only wish I remembered my Spanish classes. Smiley

Thanks, too. My english is poor, but later I?ll try to make an english version. Anyway, the texts explain the actual stage of every project, but most are static or with very basic movements, or you just can control the player. It?s much more graphics development and trainning the Ren? lessons.
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Rene_G7400
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« Reply #10 on: January 06, 2009, 10:37:43 PM »

I thought you might still be able to use MOVP3 A,@A. I suppose that is out due
to the way the signals work out on the cart?

With MOVP3 A,@A you can only get data from addresses 300-3FF, (even when you're in MB1,) so that's always in the BIOS.
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Sweersa
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« Reply #11 on: January 06, 2009, 11:22:51 PM »

Thanks Rafael! I like those screen shots you got on your web site.
I only wish I remembered my Spanish classes. Smiley

Thanks, too. My english is poor, but later I?ll try to make an english version. Anyway, the texts explain the actual stage of every project, but most are static or with very basic movements, or you just can control the player. It?s much more graphics development and trainning the Ren? lessons.

Your English seems fine to me.  I wish I knew another language like a lot of the members here. 
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Gorf
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« Reply #12 on: January 07, 2009, 01:52:35 PM »

Thanks Rafael! I like those screen shots you got on your web site.
I only wish I remembered my Spanish classes. Smiley

Thanks, too. My english is poor, but later I?ll try to make an english version. Anyway, the texts explain the actual stage of every project, but most are static or with very basic movements, or you just can control the player. It?s much more graphics development and trainning the Ren? lessons.


I like the one that looks like that Imagic game, Beam Rider.


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Gorf
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« Reply #13 on: January 07, 2009, 01:53:58 PM »

I thought you might still be able to use MOVP3 A,@A. I suppose that is out due
to the way the signals work out on the cart?

With MOVP3 A,@A you can only get data from addresses 300-3FF, (even when you're in MB1,) so that's always in the BIOS.



I've figured as much. Also, I notice no clock to the cart port.


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Rene_G7400
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« Reply #14 on: January 07, 2009, 02:54:38 PM »

Also, I notice no clock to the cart port.

No, normal carts don't need that. I think you would find that only on an expansion port.
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